This invention relates to a sample-and-hold circuit arrangement comprising an input terminal, at least two switches, a capacitor, a differential amplifier and a second amplifier of the inverting type, said second amplifier having an input terminal connected to an output terminal of said differential amplifier. The input terminal of the arrangement is connected to an input of the differential amplifier via one of the switches and an output of the second amplifier is connected to an input of the differential amplifier via the second switch.
Such a sample-and-hold circuit arrangement is known from U.S. Pat. No. 3,696,305. During the hold intervals the output voltage of this circuit arrangement is hardly influenced by the offset voltage of the differential amplifier.
In this respect the offset voltage of the differential amplifier is to be understood to mean that voltage between the inputs of the differential amplifier which yields a zero signal on the output terminal of this amplifier.
However, a disadvantage of the known circuit arrangement is that its output voltage decreases to substantially zero volts during the sampling intervals. If such circuit arrangements are employed, for example, in combination with electrical memories for data processing equipment, it is often desirable that the output voltage of the arrangement during a specific sampling interval remain substantially the same as in the directly preceding hold interval.